History log of /tinycc/i386-asm.h (Results 1 - 25 of 31)
Revision Date Author Comments
# 56927167 11-Jul-2016 Michael Matz <matz@suse.de>

x86-asm: Fix lar opcode operands

lar can accept multiple sizes as well (wlx), like lsl. When using
autosize it's important to look at the destination operand first;
when it's a regi

x86-asm: Fix lar opcode operands

lar can accept multiple sizes as well (wlx), like lsl. When using
autosize it's important to look at the destination operand first;
when it's a register that one determines the size, not the input
operand.

show more ...


# e2f489aa 15-May-2016 Michael Matz <matz@suse.de>

x86-asm: Get rid of OPC_JMP and OPC_SHORTJMP

Those two insn types are nicer to handle as operand types, because
the pressure for bits on instr_type is higher than for operands.


# 58963828 15-May-2016 Michael Matz <matz@suse.de>

x86-asm: Correct mem64->xmm movq

Now we can express prefixes with 0x0fxx opcodes we can correct the
movq mem64->xmm opcode, and restrict the movq xmm->mem64 movq to
not invalidly acc

x86-asm: Correct mem64->xmm movq

Now we can express prefixes with 0x0fxx opcodes we can correct the
movq mem64->xmm opcode, and restrict the movq xmm->mem64 movq to
not invalidly accept mmx.

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# 5a222588 15-May-2016 Michael Matz <matz@suse.de>

x86-asm: Remove OPC_D16

Now that we can store prefixes even for 0x0fXX opcodes we can remove
the OPC_D16 bit.


# bde802df 15-May-2016 Michael Matz <matz@suse.de>

x86-asm: Reorganize instr_type

Disjoint instruction types don't need to be a bit field, so
introduce an enumeration (3 bits). Also the 0x0f prefix can
be expressed by a bit, doesn't

x86-asm: Reorganize instr_type

Disjoint instruction types don't need to be a bit field, so
introduce an enumeration (3 bits). Also the 0x0f prefix can
be expressed by a bit, doesn't need a byte in the opcode field.
That enables to encode further prefixes still in 16 bit.
To not have to touch all insns do some macro fiddling filtering
out a 0x0f byte in the second position.

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# ed35ac84 14-May-2016 Michael Matz <matz@suse.de>

x86-asm: Add more SSE2 instructions

In particular those that are extensions of existing mmx (or sse1)
instructions by a simple 0x66 prefix. There's one caveat for
x86-64: as we don'

x86-asm: Add more SSE2 instructions

In particular those that are extensions of existing mmx (or sse1)
instructions by a simple 0x66 prefix. There's one caveat for
x86-64: as we don't yet correctly handle the 0xf3 prefix
the movq mem64->xmm is wrong (tested in asmtest.S). Needs
some refactoring of the instr_type member.

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# f2a4cb0a 15-May-2016 Michael Matz <matz@suse.de>

x86-asm: Reject some invalid arith imm8 instruction

There were two errors in the arithmetic imm8 instruction. They accept
only REGW, and in case the user write a xxxb opcode that varian

x86-asm: Reject some invalid arith imm8 instruction

There were two errors in the arithmetic imm8 instruction. They accept
only REGW, and in case the user write a xxxb opcode that variant
needs to be rejected as well (it's not automatically rejected by REGW
in case the destination is memory).

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# 4f27e217 13-May-2016 Michael Matz <matz@suse.de>

x86-asm: Fix signed constants and opcode order

Two things: negative constants were rejected (e.g. "add $-15,%eax").
Second the insn order was such that the arithmetic IM8S forms
were

x86-asm: Fix signed constants and opcode order

Two things: negative constants were rejected (e.g. "add $-15,%eax").
Second the insn order was such that the arithmetic IM8S forms
weren't used (always the IM32 ones). Switching them prefers those
but requires a fix for size calculation in case the opcodes were
OPC_ARITH and OPC_WLX (whose size starts with 1, not zero).

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# 080ec9fa 11-May-2016 Michael Matz <matz@suse.de>

x86-asm: Consolidate insn descriptions

Use OPC_BWLX and OPC_WLX in i386-asm.h and x86_64-asm.h to
reduce number of differences between both.


# 55bd08c5 11-May-2016 Michael Matz <matz@suse.de>

x86-asm: Remove old ASM_16 code

This code was inactive since a long time (and was deactivated because
it was wrong to start with) and just clutters the sources. Remove
it.


# bd93dc69 11-May-2016 Michael Matz <matz@suse.de>

x86: Improve cmov handling

cmov can accept multi sizes, but is also a OPC_TEST opcode,
deal with this.


# 5e47b08d 09-May-2016 Michael Matz <matz@suse.de>

[x86] Fix some asm problems

A bag of assembler fixes, to be either compatible with GAS
(e.g. order of 'test' operands), accept more instructions,
count correct foo{bwlq} variants on

[x86] Fix some asm problems

A bag of assembler fixes, to be either compatible with GAS
(e.g. order of 'test' operands), accept more instructions,
count correct foo{bwlq} variants on x86_64, fix modrm/sib bytes
on x86_64 to not use %rip relative addressing mode, to not use
invalid insns in tests/asmtest.S for x86_64.

Result is that now output of GAS and of tcc on tests/asmtest.S
is mostly the same.

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# 78ee3759 02-May-2016 Michael Matz <matz@suse.de>

x86-asm: Fix lcall/ljmp, xchg and inc/dec

Various x86 asm fixes: 64bit lcall/ljmp like 32bit a commit before,
xchgw accepted wrong operands on 32 and 64bit, and 64bit used
0x40/0x48+

x86-asm: Fix lcall/ljmp, xchg and inc/dec

Various x86 asm fixes: 64bit lcall/ljmp like 32bit a commit before,
xchgw accepted wrong operands on 32 and 64bit, and 64bit used
0x40/0x48+reg for incw/decw, but those are REX prefixes, not
instructions.

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# d1515a05 01-May-2016 Michael Matz <matz@suse.de>

i386-asm: correct lcall/ljmp encoding

The 0xff/3 form of lcall needs a mod/rm byte, so reflect this.


# 09a78412 01-May-2016 seyko <seyko2@gmail.com>

lcall hex code correction


# eb870b00 23-Sep-2015 seyko <seyko2@gmail.com>

SSE opcodes to TCC assembler (i386, x86_64)

patch from Anaël Seghezzi
a test program:
============================
#include <stdio.h>
struct fl4{ float x,

SSE opcodes to TCC assembler (i386, x86_64)

patch from Anaël Seghezzi
a test program:
============================
#include <stdio.h>
struct fl4{ float x, y, z, w; };
void asm_test(void)
{
struct fl4 v1, v2, v3;
v1.x = 0.1;
v1.y = 0.2;
v1.z = 0.4;
v1.w = 0.3;
v2.x = 0.11;
v2.y = 0.0;
v2.z = 0.01;
v2.w = 0.04;
asm volatile (
"movups %0, %%xmm0;"
"movups %1, %%xmm1;"
"addps %%xmm1, %%xmm0;"
"movups %%xmm0, %2"
:: "g" (v1), "g" (v2), "g" (v3) : "memory");
printf("sse fl4 add : %f %f %f %f\n", v3.x, v3.y, v3.z, v3.w);
printf("expected : %f %f %f %f\n", v1.x+v2.x, v1.y+v2.y, v1.z+v2.z, v1.w+v2.w);
}
int main() { asm_test(); }
/*
sse fl4 add : 0.210000 0.200000 0.410000 0.340000
expected : 0.210000 0.200000 0.410000 0.340000
*/
============================

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# 89ad24e7 29-Jul-2015 gus knight <waddlesplash@gmail.com>

Revert all of my changes to directories & codingstyle.


# 47e06c6d 27-Jul-2015 gus knight <waddlesplash@gmail.com>

Reorganize the source tree.

* Documentation is now in "docs".
* Source code is now in "src".
* Misc. fixes here and there so that everything still works.

I think I got ev

Reorganize the source tree.

* Documentation is now in "docs".
* Source code is now in "src".
* Misc. fixes here and there so that everything still works.

I think I got everything in this commit, but I only tested this
on Linux (Make) and Windows (CMake), so I might've messed
something up on other platforms...

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# 41031221 27-Jul-2015 gus knight <waddlesplash@gmail.com>

Trim trailing spaces everywhere.


# e260b036 06-Jan-2015 seyko <seyko2@gmail.com>

Allow tcc to understand a setob,... opcodes as alias to seto,...

PS: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101122/112576.html
This is fix PR8686 for llvm: accept

Allow tcc to understand a setob,... opcodes as alias to seto,...

PS: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20101122/112576.html
This is fix PR8686 for llvm: accepting a 'b' suffix at the end
of all the setcc instructions.

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# a1a691a0 24-Sep-2013 Thomas Preud'homme <robotux@celest.fr>

Detect correct instruction with incorrect operands

Display a different warning when an instruction is recognized by tcc but
the operands found do not correspond to the constraints of the

Detect correct instruction with incorrect operands

Display a different warning when an instruction is recognized by tcc but
the operands found do not correspond to the constraints of the
instruction.

show more ...


# 1b85b550 24-Feb-2011 Joe Soroka <gits@joesoroka.com>

i386-asm: support "pause" opcode


# 47b4cf22 01-Feb-2011 Joe Soroka <gits@joesoroka.com>

tccasm: accept "fmul/fadd st(0),st(n)" (dietlibc ipow/atanh)


# 87d84b7c 01-Feb-2011 Joe Soroka <gits@joesoroka.com>

tccasm: allow one-line prefix+op things like "rep stosb"


# 2047f883 21-Jan-2011 Joe Soroka <gits@joesoroka.com>

i386-asm: accept retl as a synonym for ret


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